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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\npc\Desktop\riscv\gao_yun_psram\impl\gwsynthesis\GY_riscv.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\npc\Desktop\riscv\gao_yun_psram\CST\PIN.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>C:\Users\npc\Desktop\riscv\gao_yun_psram\CST\time.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Jan 24 18:40:59 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C C6/I5</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C C6/I5</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>3620</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>3286</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>129</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>98</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>input_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk </td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F </td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n1001_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n1001_s1/F </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>input_clk</td>
<td>50.000(MHz)</td>
<td style="color: #FF0000;">47.988(MHz)</td>
<td>12</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>input_clk</td>
<td>50.000(MHz)</td>
<td style="color: #FF0000;">47.988(MHz)</td>
<td>1</td>
<td>picorv32_core/riscv32_alu_u1 </td>
</tr>
</table>
<h4>No timing paths to get frequency of picorv32_core/riscv32_alu_u1/n337_5!</h4>
<h4>No timing paths to get frequency of picorv32_core/riscv32_alu_u1/n1001_5!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>input_clk</td>
<td>Setup</td>
<td>-1.230</td>
<td>3</td>
</tr>
<tr>
<td>input_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n1001_5</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>picorv32_core/riscv32_alu_u1/n1001_5</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-5.600</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.927</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-5.569</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.896</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-5.418</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.745</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-5.013</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.340</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-4.848</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.175</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-4.824</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.151</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-4.799</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.126</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-4.794</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.121</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-4.781</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.108</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-4.753</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.080</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-4.657</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.985</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-4.613</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.940</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-4.607</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.934</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-4.423</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.750</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-4.393</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.720</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-4.279</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_5_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.606</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-4.176</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.503</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-4.176</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.503</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-4.163</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.490</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-4.080</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.407</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-4.080</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.407</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-4.080</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.407</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-3.974</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.301</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-3.938</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.265</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-3.832</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_28_s0/D</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.159</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.708</td>
<td>psram_u0/qpi_delay_cnt_0_s1/Q</td>
<td>psram_u0/qpi_delay_cnt_0_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>2</td>
<td>0.708</td>
<td>psram_u0/qpi_delay_cnt_2_s1/Q</td>
<td>psram_u0/qpi_delay_cnt_2_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>3</td>
<td>0.708</td>
<td>psram_u0/data_count_2_s0/Q</td>
<td>psram_u0/data_count_2_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>4</td>
<td>0.708</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/Q</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>5</td>
<td>0.708</td>
<td>uart_memory_u1/uart_wdata_7_s1/Q</td>
<td>uart_memory_u1/uart_wdata_7_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>6</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>7</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>8</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>9</td>
<td>0.708</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0/Q</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>10</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>11</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>12</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>13</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>14</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>15</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>16</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>17</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>18</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>19</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>20</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>21</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>22</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>23</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>24</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1/Q</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>25</td>
<td>0.708</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0/D</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-4.797</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.481</td>
</tr>
<tr style="color: #FF0000;">
<td>2</td>
<td>-4.653</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.337</td>
</tr>
<tr style="color: #FF0000;">
<td>3</td>
<td>-4.653</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.337</td>
</tr>
<tr style="color: #FF0000;">
<td>4</td>
<td>-4.644</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.327</td>
</tr>
<tr style="color: #FF0000;">
<td>5</td>
<td>-4.644</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.327</td>
</tr>
<tr style="color: #FF0000;">
<td>6</td>
<td>-4.639</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.323</td>
</tr>
<tr style="color: #FF0000;">
<td>7</td>
<td>-4.639</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>14.323</td>
</tr>
<tr style="color: #FF0000;">
<td>8</td>
<td>-4.169</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.853</td>
</tr>
<tr style="color: #FF0000;">
<td>9</td>
<td>-4.169</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.853</td>
</tr>
<tr style="color: #FF0000;">
<td>10</td>
<td>-4.169</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.853</td>
</tr>
<tr style="color: #FF0000;">
<td>11</td>
<td>-4.169</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.853</td>
</tr>
<tr style="color: #FF0000;">
<td>12</td>
<td>-4.164</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.848</td>
</tr>
<tr style="color: #FF0000;">
<td>13</td>
<td>-4.164</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.848</td>
</tr>
<tr style="color: #FF0000;">
<td>14</td>
<td>-3.680</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.364</td>
</tr>
<tr style="color: #FF0000;">
<td>15</td>
<td>-3.680</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.364</td>
</tr>
<tr style="color: #FF0000;">
<td>16</td>
<td>-3.670</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.354</td>
</tr>
<tr style="color: #FF0000;">
<td>17</td>
<td>-3.638</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>13.322</td>
</tr>
<tr style="color: #FF0000;">
<td>18</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>19</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>20</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_22_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>21</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>22</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>23</td>
<td>-3.191</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.874</td>
</tr>
<tr style="color: #FF0000;">
<td>24</td>
<td>-3.181</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_13_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.865</td>
</tr>
<tr style="color: #FF0000;">
<td>25</td>
<td>-3.181</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
<td>10.000</td>
<td>0.243</td>
<td>12.865</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.572</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_0_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.587</td>
</tr>
<tr>
<td>2</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_1_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>3</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_2_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>4</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_3_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>5</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_4_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>6</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_5_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>7</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_6_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>8</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_7_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>9</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_8_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>10</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_9_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>11</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_10_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>12</td>
<td>0.901</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_11_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.916</td>
</tr>
<tr>
<td>13</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_12_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>14</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_13_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>15</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_14_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>16</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_15_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>17</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_16_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>18</td>
<td>0.905</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_17_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.920</td>
</tr>
<tr>
<td>19</td>
<td>1.112</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_24_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.127</td>
</tr>
<tr>
<td>20</td>
<td>1.112</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_25_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.127</td>
</tr>
<tr>
<td>21</td>
<td>1.112</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_26_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.127</td>
</tr>
<tr>
<td>22</td>
<td>1.112</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_27_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.127</td>
</tr>
<tr>
<td>23</td>
<td>1.176</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_18_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.191</td>
</tr>
<tr>
<td>24</td>
<td>1.176</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_19_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.191</td>
</tr>
<tr>
<td>25</td>
<td>1.176</td>
<td>uart_memory_u1/overtime_oe_s0/Q</td>
<td>uart_memory_u1/overtime_20_s0/CLEAR</td>
<td>input_clk:[R]</td>
<td>input_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.191</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>out_byte_7_s2</td>
</tr>
<tr>
<td>2</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>out_byte_5_s1</td>
</tr>
<tr>
<td>3</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>out_byte_1_s1</td>
</tr>
<tr>
<td>4</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>mem_rdata_r0_25_s0</td>
</tr>
<tr>
<td>5</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>mem_rdata_r0_9_s0</td>
</tr>
<tr>
<td>6</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>picorv32_core/timer_cnt_12_s0</td>
</tr>
<tr>
<td>7</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_1_s0</td>
</tr>
<tr>
<td>8</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>picorv32_core/riscv32_alu_u1/irq_mask_29_s0</td>
</tr>
<tr>
<td>9</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>picorv32_core/riscv32_alu_u1/op2num_1_s0</td>
</tr>
<tr>
<td>10</td>
<td>8.307</td>
<td>9.557</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>input_clk</td>
<td>psram_u0/psram_rdata_9_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.600</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.897</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>10.670</td>
<td>1.495</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C15</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/RAD[3]</td>
</tr>
<tr>
<td>10.930</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C15</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/DO[0]</td>
</tr>
<tr>
<td>13.038</td>
<td>2.108</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C18[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n646_s2/I0</td>
</tr>
<tr>
<td>13.860</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C18[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n646_s2/F</td>
</tr>
<tr>
<td>15.798</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n646_s0/I1</td>
</tr>
<tr>
<td>16.897</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n646_s0/F</td>
</tr>
<tr>
<td>16.897</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.200, 34.837%; route: 9.269, 62.092%; tC2Q: 0.458, 3.070%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.569</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.866</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>13.356</td>
<td>2.654</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C23[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n396_s1/I3</td>
</tr>
<tr>
<td>14.455</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C23[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n396_s1/F</td>
</tr>
<tr>
<td>16.240</td>
<td>1.784</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n396_s0/I0</td>
</tr>
<tr>
<td>16.866</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n396_s0/F</td>
</tr>
<tr>
<td>16.866</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.777, 38.783%; route: 8.660, 58.140%; tC2Q: 0.458, 3.077%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.418</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.715</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>13.366</td>
<td>2.663</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C23[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n566_s1/I3</td>
</tr>
<tr>
<td>13.992</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C23[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n566_s1/F</td>
</tr>
<tr>
<td>15.616</td>
<td>1.624</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n566_s0/I0</td>
</tr>
<tr>
<td>16.715</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n566_s0/F</td>
</tr>
<tr>
<td>16.715</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.777, 39.179%; route: 8.510, 57.712%; tC2Q: 0.458, 3.108%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-5.013</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.310</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>10.676</td>
<td>1.501</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R23C15</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_1_s0/RAD[3]</td>
</tr>
<tr>
<td>10.936</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C15</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_1_s0/DO[2]</td>
</tr>
<tr>
<td>12.389</td>
<td>1.453</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C19[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n586_s2/I0</td>
</tr>
<tr>
<td>13.488</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C19[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n586_s2/F</td>
</tr>
<tr>
<td>15.278</td>
<td>1.790</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n586_s0/I1</td>
</tr>
<tr>
<td>16.310</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n586_s0/F</td>
</tr>
<tr>
<td>16.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.410, 37.727%; route: 8.472, 59.077%; tC2Q: 0.458, 3.196%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.848</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.145</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>10.670</td>
<td>1.495</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C15</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/RAD[3]</td>
</tr>
<tr>
<td>10.930</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C15</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/DO[3]</td>
</tr>
<tr>
<td>12.549</td>
<td>1.620</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C18[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n616_s2/I0</td>
</tr>
<tr>
<td>13.175</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C18[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n616_s2/F</td>
</tr>
<tr>
<td>15.113</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n616_s0/I1</td>
</tr>
<tr>
<td>16.145</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n616_s0/F</td>
</tr>
<tr>
<td>16.145</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.937, 34.829%; route: 8.780, 61.938%; tC2Q: 0.458, 3.233%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.121</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>15.089</td>
<td>1.696</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n526_s0/I3</td>
</tr>
<tr>
<td>16.121</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n526_s0/F</td>
</tr>
<tr>
<td>16.121</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.258, 37.156%; route: 8.435, 59.605%; tC2Q: 0.458, 3.239%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.799</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.096</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>11.173</td>
<td>1.998</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R23C12</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_4_s0/RAD[3]</td>
</tr>
<tr>
<td>11.432</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C12</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_4_s0/DO[2]</td>
</tr>
<tr>
<td>13.370</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n466_s2/I0</td>
</tr>
<tr>
<td>14.192</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n466_s2/F</td>
</tr>
<tr>
<td>14.997</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n466_s0/I1</td>
</tr>
<tr>
<td>16.096</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n466_s0/F</td>
</tr>
<tr>
<td>16.096</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C17[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.200, 36.813%; route: 8.467, 59.942%; tC2Q: 0.458, 3.245%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.794</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.091</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>11.152</td>
<td>1.977</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C16</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_5_s0/RAD[3]</td>
</tr>
<tr>
<td>11.411</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C16</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_0_5_s0/DO[1]</td>
</tr>
<tr>
<td>12.232</td>
<td>0.821</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C16[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n436_s2/I1</td>
</tr>
<tr>
<td>13.054</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C16[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n436_s2/F</td>
</tr>
<tr>
<td>14.992</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n436_s0/I1</td>
</tr>
<tr>
<td>16.091</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n436_s0/F</td>
</tr>
<tr>
<td>16.091</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C19[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.200, 36.825%; route: 8.463, 59.929%; tC2Q: 0.458, 3.246%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.781</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.077</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>10.670</td>
<td>1.495</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C15</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/RAD[3]</td>
</tr>
<tr>
<td>10.930</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C15</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_0_s0/DO[2]</td>
</tr>
<tr>
<td>12.218</td>
<td>1.289</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C18[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n626_s2/I0</td>
</tr>
<tr>
<td>13.317</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C18[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n626_s2/F</td>
</tr>
<tr>
<td>15.255</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n626_s0/I1</td>
</tr>
<tr>
<td>16.077</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n626_s0/F</td>
</tr>
<tr>
<td>16.077</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.200, 36.861%; route: 8.449, 59.891%; tC2Q: 0.458, 3.249%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.753</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.050</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>13.019</td>
<td>2.317</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C24[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n556_s1/I3</td>
</tr>
<tr>
<td>13.645</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C24[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n556_s1/F</td>
</tr>
<tr>
<td>14.951</td>
<td>1.305</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n556_s0/I0</td>
</tr>
<tr>
<td>16.050</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n556_s0/F</td>
</tr>
<tr>
<td>16.050</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C20[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.777, 41.030%; route: 7.845, 55.715%; tC2Q: 0.458, 3.255%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.657</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.954</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.922</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n636_s0/I3</td>
</tr>
<tr>
<td>15.954</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n636_s0/F</td>
</tr>
<tr>
<td>15.954</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C20[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.258, 37.599%; route: 8.268, 59.124%; tC2Q: 0.458, 3.277%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.910</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>15.284</td>
<td>1.891</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n536_s0/I3</td>
</tr>
<tr>
<td>15.910</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n536_s0/F</td>
</tr>
<tr>
<td>15.910</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.852, 34.806%; route: 8.630, 61.907%; tC2Q: 0.458, 3.288%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.607</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.904</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>10.676</td>
<td>1.501</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R23C15</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_1_s0/RAD[3]</td>
</tr>
<tr>
<td>10.936</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C15</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_1_s0/DO[0]</td>
</tr>
<tr>
<td>12.395</td>
<td>1.459</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C19[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n606_s2/I0</td>
</tr>
<tr>
<td>13.494</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C19[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n606_s2/F</td>
</tr>
<tr>
<td>15.278</td>
<td>1.784</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n606_s0/I1</td>
</tr>
<tr>
<td>15.904</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n606_s0/F</td>
</tr>
<tr>
<td>15.904</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.004, 35.913%; route: 8.472, 60.798%; tC2Q: 0.458, 3.289%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.423</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.720</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>11.313</td>
<td>2.138</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C9</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_7_s0/RAD[3]</td>
</tr>
<tr>
<td>11.573</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C9</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_7_s0/DO[3]</td>
</tr>
<tr>
<td>13.989</td>
<td>2.417</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s2/I0</td>
</tr>
<tr>
<td>15.088</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C14[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s2/F</td>
</tr>
<tr>
<td>15.094</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s0/I1</td>
</tr>
<tr>
<td>15.720</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s0/F</td>
</tr>
<tr>
<td>15.720</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.004, 36.394%; route: 8.288, 60.273%; tC2Q: 0.458, 3.333%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.393</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.690</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>11.173</td>
<td>1.998</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R23C12</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_4_s0/RAD[3]</td>
</tr>
<tr>
<td>11.432</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R23C12</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_4_s0/DO[0]</td>
</tr>
<tr>
<td>13.370</td>
<td>1.938</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n486_s2/I0</td>
</tr>
<tr>
<td>14.172</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n486_s2/F</td>
</tr>
<tr>
<td>14.591</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n486_s0/I1</td>
</tr>
<tr>
<td>15.690</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n486_s0/F</td>
</tr>
<tr>
<td>15.690</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C16[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.180, 37.755%; route: 8.082, 58.904%; tC2Q: 0.458, 3.341%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.279</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.576</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.754</td>
<td>1.361</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n596_s0/I3</td>
</tr>
<tr>
<td>15.576</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C22[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n596_s0/F</td>
</tr>
<tr>
<td>15.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_5_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_5_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C22[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.048, 37.102%; route: 8.099, 59.530%; tC2Q: 0.458, 3.369%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.176</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.441</td>
<td>1.049</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n446_s0/I3</td>
</tr>
<tr>
<td>15.473</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n446_s0/F</td>
</tr>
<tr>
<td>15.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.258, 38.938%; route: 7.787, 57.668%; tC2Q: 0.458, 3.394%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.176</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.473</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.441</td>
<td>1.049</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n406_s0/I3</td>
</tr>
<tr>
<td>15.473</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n406_s0/F</td>
</tr>
<tr>
<td>15.473</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.258, 38.938%; route: 7.787, 57.668%; tC2Q: 0.458, 3.394%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.163</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.460</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.428</td>
<td>1.035</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n476_s0/I3</td>
</tr>
<tr>
<td>15.460</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n476_s0/F</td>
</tr>
<tr>
<td>15.460</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C13[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.258, 38.978%; route: 7.773, 57.625%; tC2Q: 0.458, 3.398%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.080</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.377</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.278</td>
<td>0.885</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n386_s0/I3</td>
</tr>
<tr>
<td>15.377</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n386_s0/F</td>
</tr>
<tr>
<td>15.377</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.325, 39.718%; route: 7.624, 56.863%; tC2Q: 0.458, 3.419%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.080</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.377</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.278</td>
<td>0.885</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n356_s0/I3</td>
</tr>
<tr>
<td>15.377</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n356_s0/F</td>
</tr>
<tr>
<td>15.377</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.325, 39.718%; route: 7.624, 56.863%; tC2Q: 0.458, 3.419%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.080</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.377</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.278</td>
<td>0.885</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n346_s0/I3</td>
</tr>
<tr>
<td>15.377</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n346_s0/F</td>
</tr>
<tr>
<td>15.377</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.325, 39.718%; route: 7.624, 56.863%; tC2Q: 0.458, 3.419%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.974</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.271</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.546</td>
<td>1.843</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n546_s1/I3</td>
</tr>
<tr>
<td>13.645</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n546_s1/F</td>
</tr>
<tr>
<td>14.449</td>
<td>0.804</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n546_s0/I0</td>
</tr>
<tr>
<td>15.271</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n546_s0/F</td>
</tr>
<tr>
<td>15.271</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C19[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.973, 44.906%; route: 6.870, 51.648%; tC2Q: 0.458, 3.446%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.938</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.235</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/I2</td>
</tr>
<tr>
<td>7.137</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>82</td>
<td>R15C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_0_s2/F</td>
</tr>
<tr>
<td>9.926</td>
<td>2.789</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n23_s3/I1</td>
</tr>
<tr>
<td>10.971</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n23_s3/COUT</td>
</tr>
<tr>
<td>10.971</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/n24_s3/CIN</td>
</tr>
<tr>
<td>11.028</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n24_s3/COUT</td>
</tr>
<tr>
<td>11.028</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n25_s3/CIN</td>
</tr>
<tr>
<td>11.085</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n25_s3/COUT</td>
</tr>
<tr>
<td>11.085</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n26_s3/CIN</td>
</tr>
<tr>
<td>11.142</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n26_s3/COUT</td>
</tr>
<tr>
<td>11.142</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n27_s3/CIN</td>
</tr>
<tr>
<td>11.199</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R21C15[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n27_s3/COUT</td>
</tr>
<tr>
<td>12.571</td>
<td>1.372</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n336_s3/I0</td>
</tr>
<tr>
<td>13.393</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>R18C15[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n336_s3/F</td>
</tr>
<tr>
<td>14.609</td>
<td>1.216</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/n576_s0/I3</td>
</tr>
<tr>
<td>15.235</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n576_s0/F</td>
</tr>
<tr>
<td>15.235</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.852, 36.577%; route: 7.955, 59.968%; tC2Q: 0.458, 3.455%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.832</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.129</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.297</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_28_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R15C16[2][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/ram_reg_raddr_3_s5/F</td>
</tr>
<tr>
<td>11.313</td>
<td>2.138</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>R24C9</td>
<td>picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_7_s0/RAD[3]</td>
</tr>
<tr>
<td>11.573</td>
<td>0.259</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R24C9</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/risc_v_reg_risc_v_reg_1_7_s0/DO[0]</td>
</tr>
<tr>
<td>13.675</td>
<td>2.103</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C15[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n366_s2/I0</td>
</tr>
<tr>
<td>14.301</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C15[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n366_s2/F</td>
</tr>
<tr>
<td>14.307</td>
<td>0.005</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/n366_s0/I1</td>
</tr>
<tr>
<td>15.129</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C15[1][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n366_s0/F</td>
</tr>
<tr>
<td>15.129</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C15[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_28_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_28_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_28_s0</td>
</tr>
<tr>
<td>11.297</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C15[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_28_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.727, 35.924%; route: 7.973, 60.593%; tC2Q: 0.458, 3.483%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>psram_u0/qpi_delay_cnt_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>psram_u0/qpi_delay_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R23C3[0][A]</td>
<td style=" font-weight:bold;">psram_u0/qpi_delay_cnt_0_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C3[0][A]</td>
<td>psram_u0/n504_s9/I2</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C3[0][A]</td>
<td style=" background: #97FFFF;">psram_u0/n504_s9/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C3[0][A]</td>
<td style=" font-weight:bold;">psram_u0/qpi_delay_cnt_0_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>psram_u0/qpi_delay_cnt_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>psram_u0/qpi_delay_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R24C3[0][A]</td>
<td style=" font-weight:bold;">psram_u0/qpi_delay_cnt_2_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C3[0][A]</td>
<td>psram_u0/n500_s15/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R24C3[0][A]</td>
<td style=" background: #97FFFF;">psram_u0/n500_s15/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C3[0][A]</td>
<td style=" font-weight:bold;">psram_u0/qpi_delay_cnt_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R24C3[0][A]</td>
<td>psram_u0/qpi_delay_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>psram_u0/data_count_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>psram_u0/data_count_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C5[1][A]</td>
<td>psram_u0/data_count_2_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R24C5[1][A]</td>
<td style=" font-weight:bold;">psram_u0/data_count_2_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C5[1][A]</td>
<td>psram_u0/n506_s15/I3</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R24C5[1][A]</td>
<td style=" background: #97FFFF;">psram_u0/n506_s15/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R24C5[1][A]</td>
<td style=" font-weight:bold;">psram_u0/data_count_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C5[1][A]</td>
<td>psram_u0/data_count_2_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R24C5[1][A]</td>
<td>psram_u0/data_count_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C5[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C5[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_5_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C5[1][A]</td>
<td>uart_memory_u1/u_uart_recv/n83_s3/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C5[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/u_uart_recv/n83_s3/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C5[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/u_uart_recv/cnt_clk_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C5[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C5[1][A]</td>
<td>uart_memory_u1/u_uart_recv/cnt_clk_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_wdata_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_wdata_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>uart_memory_u1/uart_wdata_7_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_wdata_7_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>uart_memory_u1/n830_s6/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n830_s6/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_wdata_7_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>uart_memory_u1/uart_wdata_7_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>uart_memory_u1/uart_wdata_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C10[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R7C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_1_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C10[0][A]</td>
<td>uart_memory_u1/n55_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C10[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n55_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C10[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C10[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C11[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[1][A]</td>
<td>uart_memory_u1/n53_s1/I2</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C11[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n53_s1/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C11[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C11[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R8C10[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_7_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>uart_memory_u1/n49_s1/I2</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n49_s1/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C10[1][A]</td>
<td>uart_memory_u1/uart_delay_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_15_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>uart_memory_u1/n41_s1/I2</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" background: #97FFFF;">uart_memory_u1/n41_s1/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/uart_delay_cnt_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>uart_memory_u1/uart_delay_cnt_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C25[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_6_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9099_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R25C25[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9099_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C25[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_6_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R21C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_7_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9098_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C27[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9098_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_7_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R23C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_8_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9097_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C26[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9097_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_8_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R22C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_9_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9096_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C26[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9096_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_9_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R21C27[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_13_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9092_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C27[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9092_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C27[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_13_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C27[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C27[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_13_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R22C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_18_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9087_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C28[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9087_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_18_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_18_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C24[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_19_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9086_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R25C24[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9086_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C24[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_19_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C24[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_19_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R22C26[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_20_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9085_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C26[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9085_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C26[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_20_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C26[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C26[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_20_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_21_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9084_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9084_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_21_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_21_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_24_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9081_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C26[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9081_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C26[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_24_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C26[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_24_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R22C28[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_25_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9080_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9080_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_25_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C28[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_25_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C24[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_27_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9078_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C24[1][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9078_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C24[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_27_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R26C24[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_27_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_28_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9077_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9077_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_28_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_28_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R25C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_30_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n9075_s2/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n9075_s2/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/irq_x2_30_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/irq_x2_30_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R7C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/pcpi_valid_s1/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n8164_s10/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R7C15[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n8164_s10/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/pcpi_valid_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/pcpi_valid_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.264</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.556</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R6C25[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/jump_offset_1_s0/Q</td>
</tr>
<tr>
<td>1.892</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/n8644_s8/I1</td>
</tr>
<tr>
<td>2.264</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R6C25[0][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n8644_s8/F</td>
</tr>
<tr>
<td>2.264</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C25[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/jump_offset_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0/CLK</td>
</tr>
<tr>
<td>1.556</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C25[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/jump_offset_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.797</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.451</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.451</td>
<td>3.592</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.304%; route: 9.345, 64.531%; tC2Q: 0.458, 3.165%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.307</td>
<td>3.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.628%; route: 9.201, 64.175%; tC2Q: 0.458, 3.197%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.653</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.307</td>
<td>3.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.628%; route: 9.201, 64.175%; tC2Q: 0.458, 3.197%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.644</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.297</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.297</td>
<td>3.438</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C20[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.651%; route: 9.191, 64.150%; tC2Q: 0.458, 3.199%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.644</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.297</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.297</td>
<td>3.438</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C20[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C20[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.651%; route: 9.191, 64.150%; tC2Q: 0.458, 3.199%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.639</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.293</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.293</td>
<td>3.434</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C19[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.661%; route: 9.186, 64.139%; tC2Q: 0.458, 3.200%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.639</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.293</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>16.293</td>
<td>3.434</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C19[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C19[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 32.661%; route: 9.186, 64.139%; tC2Q: 0.458, 3.200%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.169</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.822</td>
<td>2.963</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.770%; route: 8.716, 62.922%; tC2Q: 0.458, 3.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.169</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.822</td>
<td>2.963</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.770%; route: 8.716, 62.922%; tC2Q: 0.458, 3.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.169</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.822</td>
<td>2.963</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.770%; route: 8.716, 62.922%; tC2Q: 0.458, 3.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.169</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.822</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.822</td>
<td>2.963</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.770%; route: 8.716, 62.922%; tC2Q: 0.458, 3.309%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.164</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.818</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.818</td>
<td>2.959</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C17[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.781%; route: 8.712, 62.909%; tC2Q: 0.458, 3.310%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-4.164</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.818</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.818</td>
<td>2.959</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 33.781%; route: 8.712, 62.909%; tC2Q: 0.458, 3.310%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.680</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.333</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.333</td>
<td>2.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C16[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 35.006%; route: 8.227, 61.565%; tC2Q: 0.458, 3.430%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.680</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.333</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.333</td>
<td>2.474</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C16[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 35.006%; route: 8.227, 61.565%; tC2Q: 0.458, 3.430%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.670</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.324</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.324</td>
<td>2.464</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C19[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C19[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 35.031%; route: 8.217, 61.536%; tC2Q: 0.458, 3.432%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.638</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>15.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>15.292</td>
<td>2.433</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C13[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C13[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 35.115%; route: 8.186, 61.444%; tC2Q: 0.458, 3.440%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_31_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C17[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_22_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_22_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C17[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[1][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_26_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[1][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_29_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.191</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.844</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.844</td>
<td>1.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C14[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C14[2][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_30_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.336%; route: 7.738, 60.104%; tC2Q: 0.458, 3.560%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.181</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.834</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.834</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C15[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_13_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_13_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R16C15[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.363%; route: 7.728, 60.074%; tC2Q: 0.458, 3.563%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.181</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>14.834</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>11.654</td>
</tr>
<tr>
<td class="label">From</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>picorv32_core/riscv32_alu_u1/n337_5:[F]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.970</td>
<td>0.988</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C15[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/cpu_state_0_s0/CLK</td>
</tr>
<tr>
<td>2.428</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>77</td>
<td>R11C15[0][B]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/cpu_state_0_s0/Q</td>
</tr>
<tr>
<td>3.833</td>
<td>1.405</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[0][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/I0</td>
</tr>
<tr>
<td>4.932</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R15C16[0][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_4_s1/F</td>
</tr>
<tr>
<td>6.105</td>
<td>1.173</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C22[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/I2</td>
</tr>
<tr>
<td>7.204</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R15C22[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/reg_raddr_2_s0/F</td>
</tr>
<tr>
<td>8.353</td>
<td>1.149</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C16[3][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s6/I3</td>
</tr>
<tr>
<td>9.175</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C16[3][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s6/F</td>
</tr>
<tr>
<td>9.671</td>
<td>0.496</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C18[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s7/I3</td>
</tr>
<tr>
<td>10.703</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R15C18[2][B]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s7/F</td>
</tr>
<tr>
<td>12.233</td>
<td>1.530</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C22[3][A]</td>
<td>picorv32_core/riscv32_alu_u1/n22_s3/I2</td>
</tr>
<tr>
<td>12.859</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>33</td>
<td>R17C22[3][A]</td>
<td style=" background: #97FFFF;">picorv32_core/riscv32_alu_u1/n22_s3/F</td>
</tr>
<tr>
<td>14.834</td>
<td>1.975</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td style=" font-weight:bold;">picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/n337_5</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>32</td>
<td>R18C15[2][B]</td>
<td>picorv32_core/riscv32_alu_u1/n337_s1/F</td>
</tr>
<tr>
<td>11.727</td>
<td>1.727</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C16[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0/G</td>
</tr>
<tr>
<td>11.697</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
<tr>
<td>11.654</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C16[0][A]</td>
<td>picorv32_core/riscv32_alu_u1/reg_rdata_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.243</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 49.846%; route: 0.988, 50.154%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.678, 36.363%; route: 7.728, 60.074%; tC2Q: 0.458, 3.563%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.727, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.572</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.143</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.143</td>
<td>0.254</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[2][A]</td>
<td>uart_memory_u1/overtime_0_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C7[2][A]</td>
<td>uart_memory_u1/overtime_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.254, 43.202%; tC2Q: 0.333, 56.798%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[0][B]</td>
<td>uart_memory_u1/overtime_1_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[0][B]</td>
<td>uart_memory_u1/overtime_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[1][A]</td>
<td>uart_memory_u1/overtime_2_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[1][A]</td>
<td>uart_memory_u1/overtime_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[1][B]</td>
<td>uart_memory_u1/overtime_3_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[1][B]</td>
<td>uart_memory_u1/overtime_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][A]</td>
<td>uart_memory_u1/overtime_4_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[2][A]</td>
<td>uart_memory_u1/overtime_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][B]</td>
<td>uart_memory_u1/overtime_5_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[2][B]</td>
<td>uart_memory_u1/overtime_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[0][A]</td>
<td>uart_memory_u1/overtime_6_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[0][A]</td>
<td>uart_memory_u1/overtime_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[0][B]</td>
<td>uart_memory_u1/overtime_7_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[0][B]</td>
<td>uart_memory_u1/overtime_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[1][A]</td>
<td>uart_memory_u1/overtime_8_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[1][A]</td>
<td>uart_memory_u1/overtime_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[1][B]</td>
<td>uart_memory_u1/overtime_9_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[1][B]</td>
<td>uart_memory_u1/overtime_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[2][A]</td>
<td>uart_memory_u1/overtime_10_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[2][A]</td>
<td>uart_memory_u1/overtime_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.472</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.472</td>
<td>0.583</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C8[2][B]</td>
<td>uart_memory_u1/overtime_11_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C8[2][B]</td>
<td>uart_memory_u1/overtime_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.583, 63.608%; tC2Q: 0.333, 36.392%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][A]</td>
<td>uart_memory_u1/overtime_12_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[0][A]</td>
<td>uart_memory_u1/overtime_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>uart_memory_u1/overtime_13_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[0][B]</td>
<td>uart_memory_u1/overtime_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>uart_memory_u1/overtime_14_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[1][A]</td>
<td>uart_memory_u1/overtime_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>uart_memory_u1/overtime_15_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[1][B]</td>
<td>uart_memory_u1/overtime_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>uart_memory_u1/overtime_16_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[2][A]</td>
<td>uart_memory_u1/overtime_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.905</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.476</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.476</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>uart_memory_u1/overtime_17_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C9[2][B]</td>
<td>uart_memory_u1/overtime_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.586, 63.756%; tC2Q: 0.333, 36.244%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.112</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.683</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.683</td>
<td>0.794</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_24_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[0][A]</td>
<td>uart_memory_u1/overtime_24_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C11[0][A]</td>
<td>uart_memory_u1/overtime_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.794, 70.429%; tC2Q: 0.333, 29.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.112</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.683</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_25_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.683</td>
<td>0.794</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_25_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[0][B]</td>
<td>uart_memory_u1/overtime_25_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C11[0][B]</td>
<td>uart_memory_u1/overtime_25_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.794, 70.429%; tC2Q: 0.333, 29.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.112</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.683</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.683</td>
<td>0.794</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_26_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[1][A]</td>
<td>uart_memory_u1/overtime_26_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C11[1][A]</td>
<td>uart_memory_u1/overtime_26_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.794, 70.429%; tC2Q: 0.333, 29.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.112</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.683</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_27_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.683</td>
<td>0.794</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[1][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_27_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C11[1][B]</td>
<td>uart_memory_u1/overtime_27_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C11[1][B]</td>
<td>uart_memory_u1/overtime_27_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.794, 70.429%; tC2Q: 0.333, 29.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.747</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.747</td>
<td>0.858</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>uart_memory_u1/overtime_18_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[0][A]</td>
<td>uart_memory_u1/overtime_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.858, 72.011%; tC2Q: 0.333, 27.989%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.747</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.747</td>
<td>0.858</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[0][B]</td>
<td>uart_memory_u1/overtime_19_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[0][B]</td>
<td>uart_memory_u1/overtime_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.858, 72.011%; tC2Q: 0.333, 27.989%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.176</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.747</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.571</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart_memory_u1/overtime_oe_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>input_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>input_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C7[0][A]</td>
<td>uart_memory_u1/overtime_oe_s0/CLK</td>
</tr>
<tr>
<td>1.889</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>30</td>
<td>R14C7[0][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_oe_s0/Q</td>
</tr>
<tr>
<td>2.747</td>
<td>0.858</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td style=" font-weight:bold;">uart_memory_u1/overtime_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>1186</td>
<td>IOR17[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>uart_memory_u1/overtime_20_s0/CLK</td>
</tr>
<tr>
<td>1.571</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C10[1][A]</td>
<td>uart_memory_u1/overtime_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.858, 72.011%; tC2Q: 0.333, 27.989%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 54.267%; route: 0.712, 45.733%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_7_s2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_7_s2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_7_s2/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_5_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_5_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_5_s1/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>out_byte_1_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>out_byte_1_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>out_byte_1_s1/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mem_rdata_r0_25_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>mem_rdata_r0_25_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>mem_rdata_r0_25_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>mem_rdata_r0_9_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>mem_rdata_r0_9_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>mem_rdata_r0_9_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/timer_cnt_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/timer_cnt_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/timer_cnt_12_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/uart_debug_u1/u_uart_txd/cnt_clk_1_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/riscv32_alu_u1/irq_mask_29_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/riscv32_alu_u1/irq_mask_29_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/riscv32_alu_u1/irq_mask_29_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>picorv32_core/riscv32_alu_u1/op2num_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>picorv32_core/riscv32_alu_u1/op2num_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>picorv32_core/riscv32_alu_u1/op2num_1_s0/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>8.307</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>9.557</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>input_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>psram_u0/psram_rdata_9_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.999</td>
<td>1.014</td>
<td>tNET</td>
<td>FF</td>
<td>psram_u0/psram_rdata_9_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>input_clk</td>
</tr>
<tr>
<td>20.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>20.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>21.556</td>
<td>0.712</td>
<td>tNET</td>
<td>RR</td>
<td>psram_u0/psram_rdata_9_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>1186</td>
<td>clk_d</td>
<td>-5.600</td>
<td>1.499</td>
</tr>
<tr>
<td>331</td>
<td>cpu_reset</td>
<td>8.501</td>
<td>3.603</td>
</tr>
<tr>
<td>278</td>
<td>is_csrrs_ins</td>
<td>1.194</td>
<td>5.400</td>
</tr>
<tr>
<td>148</td>
<td>cpu_state[2]</td>
<td>-4.949</td>
<td>4.344</td>
</tr>
<tr>
<td>146</td>
<td>is_csrrw_ins</td>
<td>1.436</td>
<td>4.614</td>
</tr>
<tr>
<td>127</td>
<td>cpu_state[1]</td>
<td>-5.238</td>
<td>4.155</td>
</tr>
<tr>
<td>111</td>
<td>op2num[2]</td>
<td>-0.839</td>
<td>3.641</td>
</tr>
<tr>
<td>104</td>
<td>n2040_5</td>
<td>7.270</td>
<td>3.596</td>
</tr>
<tr>
<td>101</td>
<td>irq_flag_4</td>
<td>-4.168</td>
<td>4.476</td>
</tr>
<tr>
<td>98</td>
<td>op2num[3]</td>
<td>1.229</td>
<td>3.608</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R13C21</td>
<td>95.83%</td>
</tr>
<tr>
<td>R8C25</td>
<td>90.28%</td>
</tr>
<tr>
<td>R15C36</td>
<td>90.28%</td>
</tr>
<tr>
<td>R11C21</td>
<td>88.89%</td>
</tr>
<tr>
<td>R13C10</td>
<td>88.89%</td>
</tr>
<tr>
<td>R24C7</td>
<td>88.89%</td>
</tr>
<tr>
<td>R15C22</td>
<td>88.89%</td>
</tr>
<tr>
<td>R16C33</td>
<td>88.89%</td>
</tr>
<tr>
<td>R12C25</td>
<td>87.50%</td>
</tr>
<tr>
<td>R17C37</td>
<td>87.50%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name input_clk -period 20 -waveform {0 10} [get_ports {clk}]</td>
</tr>
</table>
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